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Version 2.0, 5 May 2010
CCM-PFC
ICE3PCS01G
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)
Pow e r M a na ge m e nt & S upply
CCM-PFC Revision History: Datasheet
Edition 2010-05-05 Published by Infineon Technologies AG 81726 Munich, Germany (c) Infineon Technologies AG 05/05/10. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
CCM-PFC
ICE3PCS01G
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)
Product Highlights
* * * * * * * * High efficiency over the whole load range Lowest count of external components Accurate and adjustable switching frequency Bulk voltage good signal for inrush relay control or PWM IC enabling Integrated digital voltage loop compensation Fast output dynamic response during load jump External synchronization Extra low peak current limitation
ICE3PCS01G
PG-DSO-14
Features
* * * * * * * * * * * Continuous current operation mode PFC Wide input range of Vcc up to 25V Programmable boost follower step level according to input line and output power conditions Enhanced dynamic response without input current distortion Accurate brown-out protection threshold External current loop compensation for greater user flexibility Open loop protection Second over bulk voltage protection PFC enable function Separate signal and power ground pins Maximum duty cycle of 95% (typical)
Description
The ICE3PCS01G is a 14-pins wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC.
D BYP R NTC LBoos t DB
90 ~ 270 Vac
Line Filter
V CC CE R SHUNT
R GATE RGS
CB
RBVS 1
R BVS 4 R BVS 5
R BVS 2
R BVS 3 DBRO1 DBRO2 Qrel RCS
R BVS 6
RRel RBRO1 RBRO2 VB_OK ISENSE GATE PGND VSENSE OVP PWM Feedback
BOP RBRO3 BOFO SGND VREF R VB 1
V CC
RBOFO 1 VBTHL_EN FREQ ICOMP VCC
CBRO
RBOFO 2
RVB 2
RFREQ
CICOMP
CVCC
Type ICE3PCS01G
Version 2.0
Package PG-DSO-14
3 5 May 2010
CCM-PFC ICE3PCS01G
1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 3.9 3.10 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Setting and External Synchronization . . . . . . . . . . . . . . . . . . . . Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage Brownout Protection(BOP) . . . . . . . . . . . . . . . . . . . . . . . . Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . First Over-Voltage Protection (OVP1) . . . . . . . . . . . . . . . . . . . . . . . . . . Second Over Voltage Protection (OVP2) . . . . . . . . . . . . . . . . . . . . . . . . Bulk Voltage Monitor and Enable Function . . . . . . . . . . . . . . . . . . . . . . Boost Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PFC Brownout Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boost Follower Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 14 14 14 14 14 14 15 16 17 17 18 18 18 19 19 19 20 20 20 21
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4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 5 Bulk Voltage Good Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Pin Configuration and Functionality
1
1.1
Pin Configuration and Functionality
Pin Configuration
Function Boost Follower Setting Current Sense Input Signal Ground Current Loop Compensation Switching Frequency Setting Bulk Voltage OK signal Voltage Reference Brownout Protection Over Voltage Protection Bulk Voltage Sense IC Supply Voltage Gate Drive Power Ground SGND (Signal Ground) The ground potential of the IC. ICOMP (Current Loop Compensation) Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA6 and averages the current sense signal. FREQ (Frequency Setting) This pin allows the setting of the operating switching frequency by connecting a resistor to ground. The frequency range is from 21kHz to 250kHz. VB_OK (Bulk Voltage OK signal) This pin is pulled up to 5V internally once the bulk voltage is higher than 95% rated voltage and pulled down to ground once VSENSE pin is lower than preset VBTHL_EN threshold. This signal can enable the PWM IC or control the inrush relay. VBTHL_EN An external voltage reference can be applied to VBTHL_EN to set the turn-off threshold of VB_OK signal. The IC can be shut down by pulling the pin lower than 0.5V VREF (Voltage Reference) This pin is the 5V regulator output with a 5mA sourcing current (minimum).
1.2
Pin Functionality
Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BOFO ISENSE SGND ICOMP FREQ VB_OK VREF BOP OVP VSENSE VCC GATE PGND
BOFO (Boost Follower setting) An external DC voltage to this pin indicating the PWM output power which can be set to enter the Boost follower low step. ISENSE (Current Sense Input) The ISENSE Pin senses the voltage drop at the external sense resistor (RSHUNT). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high negative voltage drop at RSHUNT, driving currents out of pin 2 which could be beyond the absolute maximum ratings. Therefore a series resistor (RCS) of around 50 is recommended in order to limit this current into the IC.
VBTHL_EN PFC Enable Function
Package PG-DSO-14
BOFO ISENSE SGND ICOMP FREQ VB_OK VBTHL_EN P-DSO-14
PGND GATE VCC VSENSE OVP BOP VREF
Figure 1
Pin Configuration (top view)
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Pin Configuration and Functionality
BOP (Brownout Protection) BOP monitors the AC input voltage for Brownout Protection and line range selection OVP A resistive voltage divider from bulk voltage to SGND can set the over voltage protection threshold. This additional OVP is able to ensure system safety operation. VSENSE VSENSE is connected via a resistive divider to the bulk voltage. The voltage of VSENSE relative to SGND represents the output voltage. The bulk voltage is monitored for voltage regulation, over voltage protection and open loop protection. VCC VCC provides the power supply of the ground related to IC section. GATE GATE is the output for driving the PFC MOSFET.Its gate drive voltage is clamped at 15V (typically). PGND (Power Ground) Gate switching ground.
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2
Figure 2
Version 2.0
DBYP LBoost CVREF
Auxiliary Supply
Block Diagram
DB R VB1 RVB2
PWM Feedback
Block Diagram
90 ~ 270 Vac
Line Filter
PWM IC or Relay
R BOFO2
R BOFO1
VCC
VREF
VBTHL_EN
VB_OK
BOFO RBVS1 RBVS4
ICE3PCS01G
D BRO1
DBRO2
R BRO1
Reference Voltage Boost Follower
Bulk Voltage Monitor
RBVS2
R BVS5
RBRO2
A functional block diagram is given in Figure 2. Note that the figure only shows the brief functional block and does not represent the implementation of the IC.
8
BOP
Brownout Protection Protection Unit
Second OVP
OVP
R BRO3 R GATE GATE
QB
CBRO
CE
PWM Logic Driver
Ramp Generator
Voltage Loop Compensation
VSENSE
CB
PGND FREQ R FREQ Oscillator/ Synchronization
Current Loop Compensation/ PCL
Nonlinear Gain
R BVS3 R BVS6
RCS
ISENSE C ICOMP CISENSE
ICOMP
SGND
R Shunt
CCM-PFC ICE3PCS01G
Block Diagram
5 May 2010
CCM-PFC ICE3PCS01G
Block Diagram Table 1 Component Rectifier Bridge CE LBoost QB DBYP DB CB DBRO1...2 RBRO1...2 RBRO3 CBRO Rshunt Cisense RCS RGATE RFREQ CICOMP RBVS1...2 RBVS3 RBVS4...5 RBVS6 RVB1 RVB2 CVREF RBOFO1...2 Bill Of Material Parameters GBU8J 100nF/X2/275V 750uH IPP60R199CP MUR360 IDT04S60C 220F/450V 1N4007 3.9M 130k 3F 30m 1nF 50 3.3 67k 4.7nF/25V 1.5M 18.85k 2M 23k 330k 200k 100nF/25V 200k
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Functional Description
3
3.1
Functional Description
General
VBULK 100% 95%
20%
The ICE3PCS01G is a 14-pins control IC for power factor correction converters. It is suitable for wide range line input applications from 85 to 265 VAC with overall efficiency above 90%. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control. The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM) resulting in a higher harmonics but still meeting the Class D requirement of IEC 1000-3-2. The outer voltage loop controls the output bulk voltage, integrated digitally within the IC. Depending on the load condition, internal PI compensation output is converted to an appropriate DC voltage which controls the amplitude of the average input current. The IC is equipped with various protection features to ensure safe operating condition for both the system and device.
VCC 26V
12V
IVCC
1.4 mA
5 mA
<6.7mA with 1nF external cap. at gate drive pin
3.5mA
VREF 5V
VB_OK 5V
OVP UVLO configuration within 50us
VREF rises to 5V with 100nF external cap. within 200us
Bulk voltage rises to 95% rated value within 200ms
Normal operation
Standby mode (VVSENSE < 0.5V or VVBTHL < 0.5V)
Figure 3
State of Operation respect to VCC
3.3
Start-up
3.2
Power Supply
An internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 12.0V and both voltages at pin 11 (VSENSE) >0.5V and pin 9 (BOP) >1.25V, the IC begins operating its gate drive and performs its startup as shown in Figure 3. If VCC drops below 11V, the IC is off. The IC will then be consuming typically 1.4mA, whereas consuming 6.7mA during normal operation The IC can be turned off and forced into standby mode by pulling down the voltage at pin 11 (VSENSE) below 0.5V or the voltage at pin 7 (VBTHL_EN) below 0.5V.
During power up when the Vout is less than 95% of the rated level, internal voltage loop output increases from initial voltage under the soft-start control. This results in a controlled linear increase of the input current from 0A thus reducing the stress in the external components. Once Vout has reached 95% of the rated level, the softstart control is released to achieve good regulation and dynamic response and VB_OK pin outputs 5V indicating PFC stage in normal operation.
3.4
Frequency Setting and External Synchronization
The IC can provide external switching frequency setting by an external resistor RFREQ and the online synchronization by external pulse signal at FREQ pin.
3.4.1 Frequency Setting The switching frequency of the PFC converter can be set with an external resistor RFREQ at FREQ pin as shown Figure 2. The pin voltage at VFREQ is typical 1V. The corresponding capacitor for the oscillator is integrated in the device and the RFREQ/frequency is given in Figure 4. The recommended operating frequency range is from 21kHz to 250kHz. As an example, a RFREQ of 67k at pin FREQ will set a switching frequency FSW of 65kHz typically.
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Functional Description 3.5
Frequency vs Resistance
260 240 220 200 180
Voltage Loop
Resistance /kohm 15 17 20 30 40 50 60 70 80 90 100
Frequency /kHz 278 249 211 141 106 86 74 62 55 49 43
Resistance /kohm 110 120 130 140 150 169 191 200 210 221 232
Frequency /kHz 40 36 34 31.5 29.5 26.2 25 23 21.2 20.2 19.2
160 140 120 100 80 60 40 20 0
10 20 30 40 50 60 70 80
The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of sigma-delta ADC which has an internal reference of 2.5V and sampling rate of 3.55kHz (typical). The voltage loop compensation is integrated digitally for better dynamic response and saving design effort. Figure 6 shows the important blocks of this voltage loop.
LBoost DB R BVS1 QB
Frequency/kHz
90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250
Resistance/kohm
Figure 4
Frequency Versus RFREQ
Rectified Input Voltage
3.4.2 External Synchronization The switching frequency can be synchronized to the external pulse signal after 6 external pulses delay once the voltage at the FREQ pin is higher than 2.5V. The synchronization means two points. Firstly, the PFC switching frequency is tracking the external pulse signal frequency. Secondly, the falling edge of the PFC signal is triggered by the rising edge of the external pulse signal. Figure 5 shows the blocks of frequency setting and synchronization. The external RSYN combined with RFREQ and the external diode DSYN can ensure pin voltage to be kept between 1.0V (clamped externally) and 5V (maximum pin voltage). If the external pulse signal has disappeared longer than 108s (typical) the switching frequency will be synchronized to internal clock set by the external resistor RFREQ.
Syn. clock IOSC 1.0V DSYN OTA7
RGATE CB
R BVS2
R BVS3
Gate Driver Current Loop + PWM Generation VIN
Sigmadelta ADC
GATE
Nonlinear Gain Notch Filter
Av(IIN )
PI Filter
2.5V
VSENSE
t
500 ns OLP
C2 a
0.5V
C1 a
OVP OVP QR Q S
2.5V 2.7V
C1 b
Figure 6
Voltage Loop
RSYN
C9 SYN
RFREQ
FREQ
2.5V/1.25V
3.5.1 Notch Filter In the PFC converter, an averaged current through the output diode of rectified sine waveform charges the output capacitor and results in a ripple voltage at the output capacitor with a frequency two times of the line frequency. In this digital PFC, a notch filter is used to remove the ripple of the sensed output voltage while keeping the rest of the signal almost uninfluenced. In this way, an accurate and fast output voltage regulation without influence of the output voltage ripple is achieved. 3.5.2 Voltage Loop Compensation The Proportion-Integration (PI) compensation of the voltage loop is integrated digitally inside the IC. The digital data out of the PI compensator is converted to analog voltage for current loop control.
Figure 5
Frequency Setting and Synchronization
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Functional Description
The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the output voltage of integrated PI compensator. This block has been designed to reduce the voltage loop dependency on the input voltage in order to support the wide input voltage range (85VAC-265VAC). Figure 7 gives the relative output power transfer curve versus the digital word from the integrated PI compensator. The output power at the input voltage of 85VAC and maximum digital word of 256 from PI compensator is set as the normative power and the power curves at different input voltage present the relative power to the normative one.
power at 85V 10.00000 power at 265V
LBoost QB
DB
Rectified Input Voltage
Rshunt
RGATE
CB
RCS Current Loop
voltage proportional to averaged Inductor current
GATE
ISENSE ICOMP
CICOMP
Gate Driver
Current Loop Compensation OTA6 5.0mS +/-50uA (linear range) S2 5V Fault
PWM Comparator
C10
RQ S
1.00000 relative output power
PWM Logic Nonlinear Gain
Input From Voltage Loop
0.10000
0.01000
0.00100
Figure 8
0.00010 0.00001 0 18 37 55 73 91 110 128 146 165 183 201 219 238 256 PI digital output
Complete System Current Loop
Figure 7
Power Transfer Curve
3.6
Average Current Control
The choke current is sensed through the voltage across the shunt resistor and averaged by the ICOMP pin capacitor so that the IC can control the choke current to track the instant variation of the input voltage. 3.6.1 Complete Current Loop The complete system current loop is shown in Figure 8. It consists of the current loop block which averages the voltage at ISENSE pin resulted from the inductor current flowing across Rshunt. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C10 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks.
3.6.2 Current Loop Compensation The compensation of the current loop is implemented at the ICOMP pin. This is OTA6 output and a capacitor CICOMP has to be installed at this node to ground (see Figure 8). Under normal mode of the operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 5V in the event of standby mode. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous mode (CCM) to achieve the power factor correction. Assuming the loop voltage is working and output voltage is kept constant, the off duty cycle DOFF for a CCM PFC system is given as:
DOFF=VIN/VOUT
From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Figure 9 shows the scheme to achieve the objective.
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Functional Description
immediately and maintained in off state for the current PWM cycle. The signal TOFFMIN resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 11.
Ramp Profile
Ave(Iin) at ICOMP
Toff _min 600ns
Current limit Latch R Q High = turn on Gate
Gate Drive
Peak current limit
SQ PWM on Latch RQ SQ
t
Figure 9
Average Current Control in CCM
Current loop PWM on signal
The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 4 (ICOMP). The PWM cycles starts with the Gate turn off for a duration of TOFFMIN (600ns typ.) and the ramp is kept discharged. The ramp is allowed to rise after the TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 10 shows the timing diagrams of the TOFFMIN and the gate waveforms.
Toff _min 600 ns Clock PWM Cycle
Figure 11
PWM LOGIC
3.8
System Protection
The IC provides numerous protection features in order to ensure the PFC system in safe operation. 3.8.1 Input Voltage Brownout Protection(BOP) Brownout occurs when the input voltage VIN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system without BOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. ICE3PCS01G provides a new BOP feature whereby it senses directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network shown in Figure 12. This network provides a filtered value of VIN which turns the IC on when the voltage at pin 9 (BOP) is more than 1.25V. The IC enters into the fault mode when BOP goes below 1.0V. The hysteresis prevents the system to oscillate between normal and fault mode. Note also that the peak of VIN needs to be at least 20% of the rated VOUT in order to overcome OLP and powerup system.
VC,ref
(1)
Vram p Ramp Released GATE
t
(1)
V c,ref is a function of V ICOMP
Figure 10
Ramp and PWM waveforms
3.7
PWM Logic
The PWM logic block prioritizes the control input signal and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output under 65kHz of operation. In case of high input currents which results in Peak Current Limitation, the GATE will be turned off
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CCM-PFC ICE3PCS01G
Functional Description
VSENSE pin with respect to a reference voltage of 2.7V. A VSENSE voltage higher than 2.7V will immediately turn off the gate, thereby preventing damage to bus capacitor. After bulk voltage falls below the rated value, gate drive resumes switching again. 3.8.5 Second Over Voltage Protection (OVP2) The second OVP is provided in case that the first one fails due to the aging or incorrect resistors connected to the VSENSE pin. This is implemented by sensing the voltage at pin OVP with respect to a reference voltage of 2.5V. When voltage at OVP pin is higher than 2.5V, the IC will immediately turn off the gate, thereby preventing damage to bus capacitor. When the bulk voltage drops out of the hysteresis the IC can be latched further or begin auto soft-start. These two protection modes are distinguished through detecting the external equivalent resistance connecting to VBTHL_EN pin after Vcc is higher than UVLO threshold as shown in Figure 3. If the equivalent resistance is higher than 100k the IC selects latch mode for second OVP, otherwise auto soft-start mode. In normal operation the trigger level of second OVP should be designed higher than the first. However in the condition of mains transient overshoot the bulk voltage may be pulled up to the peak value of mains that is higher than the threshold of OVP1 and OVP2. In this case the OVP1 and OVP2 are triggered in the same time the IC will shut down the gate drive until bulk voltage falls out of the two protection hysteresis, then resume the gate drive again. Bulk Voltage Monitor and Enable Function The IC monitors the bulk voltage through VSENSE pin and output a TTL signal to enable PWM IC or control inrush relay. During soft-start, once the bulk voltage is higher than 95% rated value, pin VB_OK outputs a high level. The threshold to trigger the low level is decided by the pin VBTHL_EN voltage which can be adjustable externally. When pin VBTHL_EN is pulled down externally lower than 0.5V, IC will enters into standby mode and most of the function blocks are turned off. When the disable signal is released the IC recovers by soft-start. 3.8.7 Boost Follower The IC provides adjustable lower bulk voltage in case of low line input and light output power. The low line condition is determined when pin BOP voltage is less than 2.3V. Pin BOFO is connected to PWM feedback voltage through a voltage divider, representing the output power. The light load condition is determined when pin BOFO voltage is less than 0.5V. Once these two conditions are met in the same time, a 20A current source is flowing out of pin VSENSE so that the bulk voltage should be reduced to a lower level in order 3.8.6
AO2 C5
90 ~ 270 Vac
Line Filter
DBRO1
D BRO2
R BRO1
1.25V
R BRO2
BOP
C8b
Brownout Latch RQ SQ
Brownout
R BRO3
C BRO
1V
C8a
Figure 12
Input Brownout Protection
3.8.2 Peak Current Limit (PCL) The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 2 (ISENSE) reaches -0.2V. This voltage is amplified by a factor of 5 and connected to comparator with a reference voltage of 1.0V as shown in Figure 13. A deglitcher with 200ns after the comparator improves noise immunity to the activation of this protection.
Full-wave rectifier
ISENSE
R CS
G=-5 200ns
Rshunt
Iin
PCL
1V
SGND
Figure 13 Peak Current Limit (PCL) 3.8.3 Open Loop Protection (OLP) Whenever VSENSE voltage falls below 0.5V, or equivalently VOUT falls below 20% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. It is implemented using comparator C2a with a threshold of 0.5V as shown in the IC block diagram in Figure 6. 3.8.4 First Over-Voltage Protection (OVP1) Whenever VOUT exceeds the rated value by 8%, the over-voltage protection OVP1 is active as shown in Figure 6. This is implemented by sensing the voltage at
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Functional Description
to keep the VSENSE voltage same as the internal reference 2.5V as shown in Figure 14.
VCC
Reg (17V)
DBRO2 90 ~ 270 Vac DBRO1
BOP
RBRO1 RBRO2 RBRO 3
VDD
CBRO
2.3/ 2. 5V
C7
Blanking time L2H 34us H2L 1us
20uA
VBulk
RBVS1
VCC
Rpullup
RBOFO1
BOFO
0.5V
C6
Blanking time H2L 4ms L2H 32ms
VSENSE
PWM Logic HIGH to turn on
Gate Driver
LV Z1
RBVS2
External MOS
RBVS3 Opto. RBOFO2 RBOFO3 GND
GATE
* LV: Level Shift
Figure 14
Boost Follower Figure 15 Gate Driver
The reduced bulk voltage can be designed by upper side resistance of voltage divider from pin VSENSE. Thus the low side resistance is designed by the voltage divider ratio from the reference 2.5V to the rated bulk voltage. A internal 300k resistor will be paralleled with external low side resistor of BOFO pin to provide the adjustable hysteresis for PWM feedback voltage when boost follower is activated. The boost follower feature will be disabled internally during PFC soft-start in order to prevent bulk voltage oscillation due to the unstable PWM feedback voltage. This feature can also be disabled externally by pulling up pin BOFO higher than 0.5V continuously.
3.9
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 15) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 13 (GATE) is typically clamped at 15V. The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is internally pull low to maintain the off state.
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Functional Description 3.10 Protection Function
Fault-Type PCL BOP Min. Duration of Effect 200 ns 20 s 1 s 1 s 12 s 12 s Consequence Gate Driver is turned off immediately during current switching cycle Gate Driver is turned off. Soft-restart after BOP voltage > 1.25V Power down. Soft-restart after VSENSE voltage > 0.5V Disable boost follower function. Gate Driver is turned off until VSENSE voltage < 2.5V. Gate Driver is turned off until bulk voltage drops out of both OVP hysteresis Latched fault mode. Soft-restart after VCC UVLO Gate Driver is turned off. Soft-restart after OVP voltage < 2.3V Description of Fault Voltage at Pin ISENSE < -200mV Voltage at Pin BOP < 1V
Voltage at Pin VSENSE < 0.5V OLP Voltage at Pin VSENSE < 0.8V when boost follower is active Voltage at Pin VSENSE > 108% of rated level Voltage at Pin OVP > 2.5V and Voltage at Pin VSENSE > 108% of rated level Voltage at Pin OVP > 2.5V Voltage at Pin OVP > 2.5V OLP OVP1 OVP1 and OVP2 OVP2 (latch mode) OVP2 (autorestart mode)
12 s 12 s
Voltage at Pin VBTHL_EN < 0.5V after VCC > 7V Voltage at Pin VBTHL_EN > 0.5V after VCC > 7V Voltage at Pin VBTHL_EN < 0.5V when Vref outputs 5V
OVP2 mode 18 s detection OVP2 mode 18 s detection Disable function 9 s
IC enters soft-restart mode after OVP2 released. IC enters latch mode after OVP2 released. Power down. Soft-restart after disable signal is released.
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Electrical Characteristics
4
Electrical Characteristics
All voltages are measured with respect to ground (pin 3). The voltage levels are valid if other ratings are not violated.
4.1
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 12 (VCC) is discharged before assembling the application circuit.
Parameter VCC Supply Voltage GATE Voltage ISENSE Voltage ISENSE Current VSENSE Voltage VSENSE Current ICOMP Voltage FREQ Voltage VREF Voltage BOP Voltage BOP Current VB_OK Voltage VBTHL/EN Voltage BOFO Voltage OVP Voltage Junction Temperature Storage Temperature Thermal Resistance Soldering Temperature ESD Capability
1) 2) 3) 4)
Symbol Min. VVCC VGATE VISENSE IISENSE VVSENSE IVSENSE VICOMP VFREQ VVREF VBOP IBOP VVB_OK VVBTHL VBOFO VOVP TJ TA,STO RTHJA TSLD VESD -0.3 -0.3 -20 -1 -0.3 -1 -0.3 -0.3 -0.3 -0.3 -1 -0.3 -0.3 -0.3 -0.3 -40 -55
Values Typ. Max. 26 17 5.3 1 5.3 1 5.3 5.3 VVREF_0A 9.5 35 5.3 5.3 5.3 5.3 150 150 140 260 2
Unit V V V mA V mA V V V V A V V V V C C K/W C kV
Note / Test Condition
Clamped at 15V if driven internally.
1)
2)
Junction to Air Wave Soldering3) Human Body Model4)
Absolute ISENSE current should not be exceeded Absolute BOP current should not be exceeded According to JESD22A111 According to EIA/JESD22-A114-B (discharging an 100 pF capacitor through an 1.5k series resistor)
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Electrical Characteristics 4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter VCC Supply Voltage @ 25C Junction Temperature PFC switching frequency
Symbol Min. VVCC TJ FPFC VVCC,OFF -25 21
Values Typ. Max. 25 125 250
Unit V C kHz
Note / Test Condition TJ=25C
4.3
Note:
Characteristics
The electrical Characteristics involve the spread of values given within the specified supply voltage and junction temperature range TJ from -25 C to 125 C. Typical values represent the median values, which are related to 25 C. If not otherwise stated, a supply voltage of VVCC = 18V, a typical switching frequency of ffreq=65kHz are assumed and the IC operates in active mode. Furthermore, all voltages are referring to GND if not otherwise mentioned. Supply Section Symbol Min. VCCon VCCUVLO VCChy ICCstart1 ICCstart2 ICCHG ICCStdby Limit Values Typ. 12 11.0 1 380 1.4 6.7 3.5 Max. 12.9 11.9 1.45 700 2.4 9 4.7 V V V A mA mA mA VCCon-1.2V VCCon-0.2V CL= 1nF VVSENSE= 0.4V VICOMP= 4V 11.5 10.5 0.7 Unit Note/Test Condition
4.3.1
Parameter VCC Turn-On Threshold VCC Turn-Off Threshold/ Under Voltage Lock Out VCC Turn-On/Off Hysteresis Start Up Current Before VCCon Start Up Current Before VCCon Operating Current with active GATE Operating Current during Standby
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Electrical Characteristics
4.3.2 Variable Frequency Section Symbol Min. Switching Frequency (Typical) Switching Frequency (Min.) Switching Frequency (Max.) Voltage at FREQ pin Max. Duty Cycle FSWnom FSWmin FSWmax VFREQ Dmax 62.5 93 Limit Values Typ. 65 21 250 1 95 Max. 67.5 98.5 kHz kHz kHz V % fSW=fSWnom (RFRE=67k) R5 = 67k R5 = 212k R5 = 17k Unit Test Condition Parameter
4.3.3
PWM Section Symbol Min. DMIN TOFFMIN 310 600 Limit Values Typ. Max. 0 920 % ns VVSENSE= 2.5V VICOMP= 4.3V VVSENSE= 2.5V VISENSE= 0V (R5 = 67k) Unit Test Condition
Parameter Min. Duty Cycle Min. Off Time
4.3.4
External Synchronization Symbol Min. Vthr_EXT fEXT_range fEXT:fPFC TEXT2GATE 50 1:1 500 ns fEXT=65kHz Values Typ. 2.5 150 Max. V kHz Unit Note / Test Condition
Parameter Detection threshold of external clock Synchronization range Synchronization frequency ratio propagation delay from rising edge of external clock to falling edge of PFC gate drive Allowable external duty on time
TD_on
10
70
%
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Electrical Characteristics
4.3.5 PFC Brownout Protection Section Symbol Min. Input Brownout Protection High to Low Threshold Input Brownout Protection Low to High Threshold Blanking time for BOP turn_on Input Brownout Protection BOP Bias Current 4.3.6 System Protection Section Symbol Min. Over Voltage Protection (OVP1) Low to High Over Voltage Protection (OVP1) High to Low Over Voltage Protection (OVP1) Hysteresis Blanking time for OVP1 Over Voltage Protection (OVP2) Low to High Over Voltage Protection (OVP2) High to Low Blanking time for OVP2 OVP2 mode detection threshold Current source for OVP2 mode detection1) Peak Current Limitation (PCL) ISENSE Threshold Blanking time for PCL turn_on
1)
Parameter
Values Typ. 1 1.25 20 -0.5 0.5 Max. 1.02 1.3 0.98 1.2
Unit V V s A
Note / Test Condition
VBOP_H2L VBOP_L2H TBOPon IBOP
VBOP=1.25V
Parameter
Values Typ. 2.7 2.5 200 12 2.45 2.25 2.5 2.3 12 0.5 4 -180 5 -200 200 6 -220 2.55 2.35 Max. 2.77 2.55 270 2.65 2.45 150
Unit Note / Test Condition V V mV s V V s V A mV ns comparator at VBTHL pin current source at VBTHL pin 108%VBULKRated
VOVP1_L2H VOVP1_H2L VOVP1_HYS TOVP1 VOVP2_L2H IOVP2_H2L TOVP2 VOVP2_mode IOVP2_mode VPCL TPCLon
The parameter is not subject to production test - verified by design/characterization Internal Voltage Reference Symbol Min. VVREF_0A VVREF_5mA VVREF_VCC 4.9 Values Typ. 5 Max. 5.1 50 25 V mV mV IVREF=0mA IVREF=-5mA1) VCC=3V Unit Note / Test Condition
4.3.7
Parameter Output Reference Voltage Load Regulation Line Regulation
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Electrical Characteristics
Parameter Maximum Source Current Temperature Stability Total Variation
1)
Symbol Min. IVREF VVREF_temp VVREF_total 4.85 -6
Values Typ. 1.0 5.2 Max.
Unit Note / Test Condition mA % Line, Load, Temperature
Maximum pulling current depends on the maximum operating junction temperature Boost Follower Section Symbol Min. VBOFO RBOFO_hys TBOFO_L2H TBOFO_H2L VLD_H VLD_L TLD IBOFO 18.7 2.46 2.25 0.47 240 Values Typ. 0.5 300 32 4 2.5 2.3 32 20 21 2.56 2.35 Max. 0.53 360 V k ms ms V V s A Unit Note / Test Condition
4.3.8
Parameter BOFO threshold BOFO hysteresis resistor Blanking time for BOFO on Blanking time for BOFO off High line detection threshold Low line detection threshold Blanking time for line detection Current source for low step 4.3.9 Bulk Voltage Good Section
Parameter VB_OK turn-on threshold VB_OK turn-off threshold Disable function threshold Blanking time for disable function VB_OK max source current
1)
Symbol Min. VVBOKon VVBOKoff VVBTHL_EN TVBTHL_EN IVB_OKMax -1
1)
Values Typ. 2.375 VVBTHL_EN 0.45 0.5 9 0.55 Max. 2.5 2.25
Unit Note / Test Condition V V V s mA sensed at pin VSENSE set by pin VBTHL_EN
shared with the max source current of the VREF pin.
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Electrical Characteristics
4.3.10 Current Loop Section Symbol Min. OTA6 Transconductance Gain OTA6 Output Linear Range
1) 1)
Parameter
Values Typ. 5.0 50 4.8 5.0 5.2 Max. 6.35 3.5
Unit Note / Test Condition mS A V VVSENSE= 0.4V At Temp = 25C
GmOTA6 IOTA6 VICOMPF
ICOMP Voltage during OLP
The parameter is not subject to production test - verified by design/characterization Voltage Loop Section Symbol Min. VVSREF VVS_OLP IVSENSE 2.47 0.45 -1 Values Typ. 2.5 0.5 Max. 2.53 0.55 1 V V A VVSENSE= 2.5V 1.2% Unit Note / Test Condition
4.3.11
Parameter Trimmed Reference Voltage Open Loop Protection (OLP) VSENSE Threshold VSENSE Input Bias Current 4.3.12 Driver Section
Parameter GATE Low Voltage
Symbol Min. VGATEL -0.2
Values Typ. 0.4 0.8 15 12.4 Max. 1.2 1.4 -
Unit Note / Test Condition V V V V V V V VCC =10V IGATE = 5 mA IGATE = 0 A IGATE = 20 mA IGATE = -20 mA VCC = 25V CL = 1nF VCC = 15V CL = 1nF VCC = VVCCoff + 0.2V CL = 1nF
GATE High Voltage
VGATEH
8.0
4.3.13
Gate Drive Section Symbol Min. tr tf Values Typ. 30 25 Max. ns ns VGate = 20% - 80% VGATEH CL = 1nF VGate = 80% - 20% VGATEH CL = 1nF Unit Note / Test Condition
Parameter GATE Rise Time GATE Fall Time
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Outline Dimension
5
Outline Dimension
0.33 0.08 x 45
1.75 MAX.
PG-DSO-14 Outline Dimension
4 -0.2 1)
0.1 MIN. (1.5)
1.27 0.41 +0.1 -0.06 14
0.2 M
8
0.1 A C 14x
C
6 0.2
0.64 0.25
1 7 1) 8.75 -0.2
A
Index Marking
1)
Does not include plastic or metal protrusion of 0.15 max. per side
Notes: 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. 2. Dimensions in mm.
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.01
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